The ADuCM360 is a fully integrated 3.9 kSPS, 24-bit data acquisition system from ADI that integrates a dual-core, high-performance multi-channel analog-to-digital converter (ADC), 32-bit ARM Cortex-M3 processor, and Flash/EE memory on a single chip. In wired and battery-powered applications, the ADuCM360 is designed to interface directly with external precision sensors. The ADuCM361 integrates all the features of the ADuCM360, but it has only one 24-bit ADC (ADC1).
The ADuCM360/ADuCM361 comes with an on-chip 32kHz oscillator and an internal 16MHz high frequency oscillator. The high frequency oscillator is relayed by a programmable clock divider that produces the processor core clock operating frequency. The maximum core clock speed is 16 MHz; this speed is not limited to the operating voltage or temperature.
Functional block diagram
Figure 1. Functional Block Diagram of ADuCM360
Root mean square noise resolution of ADC0 and ADC11.2 V Internal References Tables 2 through 5 provide the rms noise specifications for ADC0 and ADC1 with an internal reference (1.2 V). Tables 2 and 3 list the rms noise values ​​for different gain and output update rates for the two ADCs. Table 4 and Table 5 list the typical output rms noise effective bits (ENOB) for the two ADCs in normal mode with different gain and output update rates. (The number in parentheses indicates pp ENOB)
1 ADCxMDE = 0x49 sets the gain of the PGA to 16 and the modulator gain to 2. A modulator gain of 2 is achieved by adjusting the sampling capacitor in the modulator. ADCxMDE = 0x51 sets the gain of the PGA to 32 and the modulator gain is turned off. ADCxMDE = 0x49 is slightly louder, but supports a wider input range.
2 If AVDD < 2.0 V and ADCxMDE = 0x51, the input range is ±17.5 mV.
3 ADCxMDE = 0x59 sets the gain of the PGA to 32 and the modulator gain to 2. A modulator gain of 2 is achieved by adjusting the sampling capacitor in the modulator. ADCxMDE = 0x61 sets the gain of the PGA to 64 and the modulator gain is off. ADCxMDE = 0x59 is slightly louder, but supports a wider input range.
4 If AVDD < 2.0 V and ADCxMDE = 0x61, the input range is ±8.715 mV.
5 ADCxMDE = 0x69 sets the gain of the PGA to 64 and the modulator gain to 2. A modulator gain of 2 is achieved by adjusting the sampling capacitor in the modulator. ADCxMDE = 0x71 sets the gain of the PGA to 128 and the modulator gain is turned off. ADCxMDE = 0x69 is slightly louder, but supports a wider input range.
6 If AVDD < 2.0 V and ADCxMDE = 0x71, the input range is ±3.828 mV.
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