As the number of electronic components in automobiles continues to increase, the quality of semiconductor components in modern automobiles must be strictly controlled to reduce the defect rate per million (DPM), and the use of on-site return and warranty related to electronic components must be maintained. Minimize the problem and reduce the liability problems caused by the failure of electronic components.
The demand for zero-defect semiconductor components has been rising in the industry, and semiconductor manufacturers have begun to increase investment to meet the challenges to meet the needs of automotive users.
The American Automotive Electronics Council’s AEC-Q001 specification recommends a generic method that uses the Part Average Testing (PAT) method to remove anomalous parts from the total parts, thus improving component quality at the supplier stage and reliability. For specific wafers, lot numbers, or parts to be tested, the PAT method can indicate test results where the total average value falls outside 6σ. Any test result that exceeds the 6σ limit value for a particular component is considered to be unacceptable and from the part The total number is eliminated. Parts that do not reach the PAT limit value cannot be shipped to customers. This improves the quality and reliability of the components.
User requirements for these specifications have driven the competition among suppliers to become more intense. There is great pressure to improve reliability and reduce defect rates, especially for many of the more important safety functions currently controlled by semiconductors, such as brakes, traction control, power, and active stability control systems. Suppliers need to improve the quality of parts that have already begun to ship, but also to minimize the impact of these specifications on their yield. As manufacturing costs continue to decline, the cost of testing remains at a relatively constant level. As a result, the proportion of test costs in manufacturing costs is increasing and the profit margin of components continues to shrink.
Since most of the yields cannot meet the requirements, suppliers must thoroughly evaluate their testing procedures in order to find alternative testing methods, and trial and error from alternative methods until the best method is found. Without leading-edge analysis and simulation tools, suppliers will apply them without fully understanding the impact of these specifications on the supply chain.
What's worse is that if blindly applied and misses important tests, then even if it is guaranteed that components will be tested using PAT or other specifications and shipped at the same DPM rate, the guarantee is no doubt in this case. Righteousness, but also reduce reliability. Some vendors seem to think that PAT testing in wafer probing is sufficient, but studies have shown that there are many problems with this approach. The use of PAT in wafer probing is the first quality checkpoint, but in the remaining downstream manufacturing process, due to the variable increase caused by innumerable variable factors, it will lead to more PAT outliers during package testing. If suppliers want to introduce high-quality parts, they must perform PAT testing in both wafer probing and final testing, and their customers should also promote the application of this method.
The method used for real-time PAT and statistical post-processing PAT processing is to analyze the latest data through several batch processes and establish static PAT limits for each test of interest. The average of these limits is calculated as +/- 6 sigma, and is usually incorporated into the test program as the upper specification limit (USL) and the lower specification limit (LSL). Static PAT limits must be reviewed and updated at least every six months.
The preferred method is to calculate the dynamic PAT limit for each batch or wafer. The dynamic PAT limit value is generally more stringent than the static PAT limit value and clears any outliers that are not within the normal distribution. The most important difference is that dynamic PAT limits are calculated on a wafer or batch basis, and therefore the limit value will vary continuously depending on the material properties used for the wafer or batch. The dynamic PAT limit value is calculated as mean +/- (n*σ) or median +/- (N* tough σ) and cannot be less than the LSL specified in the test procedure or greater than USL.
The calculated PAT limit value must be used as the lower PAT limit (LPL) and higher PAT limit (UPL) shown in FIG. Any value that exceeds the dynamic PAT limit and is between the LSL and USL limits is considered an outlier. These outliers are usually named faults and are loaded into a specific outlier software and hardware box. Tracking the PAT limits calculated for a particular wafer or lot and the amount of anomalies detected for each test are important for late traceability.
There are two main methods for implementing PAT: real-time PAT and statistical post-processing (SPP). Vendors must know if they want to use two different methods for detection and final testing, or whether it is more meaningful to use only one solution. Real-time PAT, based on the calculation of dynamic PAT limits, makes sorting decisions when the part is tested without affecting the test time. This requires a dynamic real-time engine capable of handling complex data streams monitored and sampled.
Similarly, this process also requires a robust statistics engine that can capture test data and perform the necessary calculations to generate new limit values, send new limit values ​​and sorting information to the test program, and monitor the entire process. To ensure stability and controllability. Vendors need to perform real-time processing of probes and final tests and handle baseline outliers. The statistical post-processing method will produce the same final test results. After a batch is completed, the component test must be statistically processed and the sorting decision made.
However, because sorting decisions are made after batch processing, post-processing can only be used for wafer probing because the test and sort results are related to specific components for re-sorting. In package testing, once the components are packaged, there is no way to track or sequence them, and it is not possible to associate test and sort results with specific components. SPP also requires data records for full test results to make decisions, increasing IT infrastructure needs (a lot of time) and significantly slowing down test time. Since the results are post-processed, the SPP processes the baseline outliers in a batch as part of the component as a whole.
Both methods need to perform powerful calculations when dealing with testing and sorting results, just like regional PAT and other failure modes. An example of regional PAT is that a qualified chip in a wafer is surrounded by multiple faulty chips.
The demand for zero-defect semiconductor components has been rising in the industry, and semiconductor manufacturers have begun to increase investment to meet the challenges to meet the needs of automotive users.
The American Automotive Electronics Council’s AEC-Q001 specification recommends a generic method that uses the Part Average Testing (PAT) method to remove anomalous parts from the total parts, thus improving component quality at the supplier stage and reliability. For specific wafers, lot numbers, or parts to be tested, the PAT method can indicate test results where the total average value falls outside 6σ. Any test result that exceeds the 6σ limit value for a particular component is considered to be unacceptable and from the part The total number is eliminated. Parts that do not reach the PAT limit value cannot be shipped to customers. This improves the quality and reliability of the components.
User requirements for these specifications have driven the competition among suppliers to become more intense. There is great pressure to improve reliability and reduce defect rates, especially for many of the more important safety functions currently controlled by semiconductors, such as brakes, traction control, power, and active stability control systems. Suppliers need to improve the quality of parts that have already begun to ship, but also to minimize the impact of these specifications on their yield. As manufacturing costs continue to decline, the cost of testing remains at a relatively constant level. As a result, the proportion of test costs in manufacturing costs is increasing and the profit margin of components continues to shrink.
Since most of the yields cannot meet the requirements, suppliers must thoroughly evaluate their testing procedures in order to find alternative testing methods, and trial and error from alternative methods until the best method is found. Without leading-edge analysis and simulation tools, suppliers will apply them without fully understanding the impact of these specifications on the supply chain.
What's worse is that if blindly applied and misses important tests, then even if it is guaranteed that components will be tested using PAT or other specifications and shipped at the same DPM rate, the guarantee is no doubt in this case. Righteousness, but also reduce reliability. Some vendors seem to think that PAT testing in wafer probing is sufficient, but studies have shown that there are many problems with this approach. The use of PAT in wafer probing is the first quality checkpoint, but in the remaining downstream manufacturing process, due to the variable increase caused by innumerable variable factors, it will lead to more PAT outliers during package testing. If suppliers want to introduce high-quality parts, they must perform PAT testing in both wafer probing and final testing, and their customers should also promote the application of this method.
The method used for real-time PAT and statistical post-processing PAT processing is to analyze the latest data through several batch processes and establish static PAT limits for each test of interest. The average of these limits is calculated as +/- 6 sigma, and is usually incorporated into the test program as the upper specification limit (USL) and the lower specification limit (LSL). Static PAT limits must be reviewed and updated at least every six months.
The preferred method is to calculate the dynamic PAT limit for each batch or wafer. The dynamic PAT limit value is generally more stringent than the static PAT limit value and clears any outliers that are not within the normal distribution. The most important difference is that dynamic PAT limits are calculated on a wafer or batch basis, and therefore the limit value will vary continuously depending on the material properties used for the wafer or batch. The dynamic PAT limit value is calculated as mean +/- (n*σ) or median +/- (N* tough σ) and cannot be less than the LSL specified in the test procedure or greater than USL.
The calculated PAT limit value must be used as the lower PAT limit (LPL) and higher PAT limit (UPL) shown in FIG. Any value that exceeds the dynamic PAT limit and is between the LSL and USL limits is considered an outlier. These outliers are usually named faults and are loaded into a specific outlier software and hardware box. Tracking the PAT limits calculated for a particular wafer or lot and the amount of anomalies detected for each test are important for late traceability.
There are two main methods for implementing PAT: real-time PAT and statistical post-processing (SPP). Vendors must know if they want to use two different methods for detection and final testing, or whether it is more meaningful to use only one solution. Real-time PAT, based on the calculation of dynamic PAT limits, makes sorting decisions when the part is tested without affecting the test time. This requires a dynamic real-time engine capable of handling complex data streams monitored and sampled.
Similarly, this process also requires a robust statistics engine that can capture test data and perform the necessary calculations to generate new limit values, send new limit values ​​and sorting information to the test program, and monitor the entire process. To ensure stability and controllability. Vendors need to perform real-time processing of probes and final tests and handle baseline outliers. The statistical post-processing method will produce the same final test results. After a batch is completed, the component test must be statistically processed and the sorting decision made.
However, because sorting decisions are made after batch processing, post-processing can only be used for wafer probing because the test and sort results are related to specific components for re-sorting. In package testing, once the components are packaged, there is no way to track or sequence them, and it is not possible to associate test and sort results with specific components. SPP also requires data records for full test results to make decisions, increasing IT infrastructure needs (a lot of time) and significantly slowing down test time. Since the results are post-processed, the SPP processes the baseline outliers in a batch as part of the component as a whole.
Both methods need to perform powerful calculations when dealing with testing and sorting results, just like regional PAT and other failure modes. An example of regional PAT is that a qualified chip in a wafer is surrounded by multiple faulty chips.
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