l Hardware design of self-destruction system The hardware design adopts a scheme that combines a digital circuit with a high-performance CPLD chip as the core and an analog circuit with high-performance operational amplifiers and flight parameter sensor groups as the main components. The system is mainly composed of modules such as system clock, CPLD control chip, flight parameter sensor group, sensor group output judgment and generation circuit, self-destruction control logic, test module and power supply. The design uses Altera's EPM7064SLC44-10 chip, which contains 64 macrocells, 1 250 available system gates, pin-to-pin logic delay time is 5.0 ns, and the counter operating frequency can reach 175. 4 MHz.
The core circuit and peripheral circuits of the timing control logic for realizing the above self-destructive conditions using CPLD are shown in FIG. 1. CPLD chip is the core of the entire system, it is used to achieve timing and timing control of the entire system. The DC voltage conversion circuit is used to convert the input DC voltage into the voltage required by the EPM7064S and the operating voltage required by the peripheral circuits. The system clock circuit provides a stable clock signal for the timing device and a clock reference for subsequent frequency division; the level conversion circuit converts the input signal on the aircraft to a TTL / CMOS level standard that the chip can recognize; the reset circuit is on the system After power on, it provides reset signal to the control chip.
The flight parameter sensor group circuit is used to monitor various indicators of the aircraft in real time. When the flight status is abnormal, the corresponding analog value is generated by the sensor group to the analog circuit with the high-performance operational amplifier and comparator as the main components. The analog circuit processes the input value of the sensor and sends it to the CPLD timing control module. The controllable switch can realize multiple conversion by programming CPLD, so as to change the monitored flight parameter sensor, and then change the self-destruction condition of the aircraft. The internal timing control of the aircraft is carried out through CPLD, and the self-destruction command output at the end is input to the flight control signal module, thereby changing the flight status of the aircraft and making it self-destruct. 2 Finite state machine model and selection
2.1 Finite state machine model Finite State Machine (Finite State Machine, FSM) can be represented by the following set of 5 elements to represent {X, Y, S, f, g}, where S = {S1, S2, ..., Sk} is the set of states in FSM; X = {X1, X2, ..., Xn} is the set of inputs in FSM; Y = {Y1, Y2, ..., Ym) is the set of outputs in FSM; f is the state transfer function , Indicating that the next state is determined by the input signal variable X and the current state S, namely: XY; → S; g is the output function, indicating that the input signal variable X and the state S determine the output variable Y of the state machine, namely: XS → Y . As can be seen from the above definition, the finite state machine contains five basic elements: state, input, output, transfer function, and output function. They are expressed as vector functions as follows:
The classification rules that are not used are different for the state machine classification. In actual applications, designers often divide them into two types, Moore finite state machine and Mealy type finite state machine, according to whether the finite state machine uses input signals. The output of the Moore type state machine is only related to the current state and not the input. The output of the Mealy type state machine is not only related to the current state, but also related to the current input. They jointly determine the output of the Mealy state machine. Figure 2 and Figure 3 show the structure diagram of Moore and Mealy state machine respectively.
There are many classification methods for finite state machines, such as synchronous reset state machine and asynchronous reset state machine according to different reset signals. According to whether the output is registered, it is divided into direct output, registered output, and output based on status code.
For the Moore-type finite state machine, the output signal will get the output value after a few gate delays to the trigger edge of the clock signal, and at the same time it will remain unchanged for the remaining time of the clock cycle, even if the input signal occurs during the clock cycle Changes, the value of the output signal will not change. Since the output of the Moore-type finite state machine has nothing to do with the current input part, any effects produced by the current input will be delayed until the next clock cycle. It can be seen that the biggest advantage of the Moore state machine is that it can isolate the input part from the output part.
For Mealy type finite state machine, since its output is a function of the input signal, if the input signal changes, the output can change in the middle of 1 clock cycle. Compared with the Moore finite state machine, it changes the input signal correspondingly 1 clock cycle earlier. But it will also pass the noise from the input port to the output signal.
Based on the above considerations, the design uses Moore finite state machine to realize the timing control of the aircraft self-destruction system.
2.2 Glitch and signal delay processing Moore-type finite state Due to the existence of combinational logic process, the state machine output signal will appear glitch (competition risk phenomenon); on the other hand, if the state signal is multi-bit value, then in the circuit There are multiple signal lines in. Due to the transmission delay, the time at which the value on each signal line changes occurs in sequence, so that a temporary state appears between the initial state and the destination state when the state transitions, so glitches occur.
With reference to various literatures, there are currently three options for eliminating the "glitch" of the output signal: First, adjust the state code so that only 1 signal changes between adjacent states, thereby eliminating the conditions for competition and risk, and avoiding the occurrence of glitches . This scheme is suitable for the state machine of sequential migration; the second is to use the clock synchronization signal on the basis of the finite state machine, that is, the clock signal is introduced into the combined process. Each output signal of the state machine passes through the additional output register and is synchronized by the clock signal, thus ensuring that the output signal has no glitches. This method has some disadvantages; due to the increase of the output register, the hardware overhead increases, which is unfavorable for some chips with fewer register resources; from the state machine's status bit to the output, it needs to go through the two-stage combinational logic, which limits The maximum operating frequency of the system clock; because the clock signal loads the output to an additional register, the time to get the signal value at the output is delayed by 1 clock cycle than the state change; the third is to directly use the state machine's status code as the output The signal, that is, a state machine that directly outputs the state code, makes the state consistent with the output signal, so that the output decoding circuit is optimized, so there will be no competition risk. This scheme takes up less chip resources, and the signal is synchronized with the state change, so the speed is fast. Therefore, the design uses the Moore type finite state machine with the reset signal as the output signal. Its structural block diagram is shown as in Fig. 4.
3 Design of finite state machine under Quartusâ…¡ environment
3.1 Overall system structure The aircraft self-destruction system starts to work after the aircraft takes off and monitors the control signals generated by the flight parameter sensor group and timing module in real time. Figure 5 shows the hardware implementation of the self-destruction control circuit. The overall structure of the system implemented in CPLD is shown in Figure 5. The high-performance operational amplifier around the CPLD is the main component of the analog circuit and sensor group used to generate timing control signals (c1, c2, c3, c4, c5), and input to the input signal processing module. The frequency division of the clock is used to generate the clock required for each module to work. The timing module is used to generate the total flight time (tmax). The timing control module is used to generate a self-destructive output signal (Output). It is the control core of the entire system. Its reliability and stability are the basis for the aircraft to achieve reliable self-destruction. The timing control module of the Moore finite state machine design with state as the output signal and reset signal is used here to achieve reliable self-destruction of the aircraft.
3.2 Improved Finite State Machine to Realize Timing Control The flow chart of the timing control of the self-destruction of the aircraft is shown in Figure 6. The timing state change of the aircraft self-destruction system is determined by the input of each sensor and the state of the CPLD timer. The flight parameter sensor group enters different state commands, and the timing control system can change between different states. The ST5 state is the control output of the entire self-destruction system. According to Figure 6, the excitation equations of five state triggers can be obtained:
Before using VHDL language to describe this improved Moore finite state machine, we must first encode the state of the Moore finite state machine. As shown in Table 1, since the output of the finite state machine is only Output, in order to better identify these five different states during synthesis, a status bit needs to be added. Add two redundant status bits a, b in Table 2 to distinguish ST1, ST2, ST3, ST4.
3.3 Precautions for VHDL programming This design adopts single process description mode, and two process descriptions can also be used. When using two processes, it is best to separate the transition condition judgment logic and the output logic, which is beneficial to the synthesizer to optimize the code, help the user to add appropriate timing constraints, and facilitate the placement and routing. The state machine must have a default state, which is considered from the Security aspect of the state machine. In the design of the state machine, it generally includes an initial state. When the chip is powered on and reset, the state machine can enter the initial state. This requires adding a reset signal to the state machine design.
4 Circuit simulation In the Quartus II environment, save the VHDL text program as a project, and the project file can be used for circuit simulation after compilation. The simulation waveform is shown in Figure 7. From the waveform results, it can be seen that the reset signal is effective to restore the state machine to the initial state, the aircraft takes off (off) effectively starts, and the timing control system has experienced five different The state is shown in the state variable in Figure 7. And finally output self-destruct instruction (Output), VHDL programming meets the requirements. The entire timing control is reliable, eliminating glitches. In the Quartus II environment, only one download programming cable is needed, which is connected to the JTAG port of the target board through the parallel port of the PC and downloads the download information to the target device.
5 Conclusion The simulation and experimental results prove that using the above finite state machine idea to design the timing control of the aircraft self-destruction system can not only reduce the CPLD resources, reduce costs, and facilitate testing, but also have good system performance. The timing accuracy of the aircraft self-destruction system based on the finite state machine reaches the nanosecond level, which can effectively and reliably control the output of the self-destruction signal, effectively eliminate glitches, and improve the stability and reliability of the aircraft self-destruction system.
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