Introduction to FPGA main function modules (1)

The function of each module is as follows:

1. Programmable input and output unit (IOB)

The programmable input/output unit is referred to as the I/O unit, which is the interface part between the chip and the external circuit. It completes the driving and matching requirements of the input/output signals under different electrical characteristics. The schematic structure is shown in Figure 2-4. The I/O within the FPGA is categorized by group, and each group can independently support different I/O standards. Through the flexible configuration of the software, different electrical standards and I/O physical characteristics can be adapted, the driving current can be adjusted, and the upper and lower pull-down resistors can be changed. Currently, the frequency of I/O ports is getting higher and higher, and some high-end FPGAs can support data rates up to 2Gbps through DDR register technology.

IOB module

Figure 2-4 Internal structure of IOB
The external input signal can be input to the FPGA through the memory unit of the IOB module or directly into the FPGA. When an external input signal is input to the FPGA through the memory location of the IOB module, the hold time (Hold TIme) requirement can be reduced, usually by default to zero. In order to manage and adapt to various electrical standards, the IOB of the FPGA is divided into several banks. The interface standard of each bank is determined by its interface voltage VCCO. A bank can only have one type of VCCO, but VCCOs of different banks can different. Only ports of the same electrical standard can be connected together, and the same VCCO voltage is the basic condition of the interface standard. 2. Configurable logic block (CLB)

CLB is the basic logical unit within the FPGA. The actual number and characteristics of CLBs will vary from device to device, but each CLB contains a configurable switch matrix consisting of 4 or 6 inputs, some sizing circuits (multiplexers, etc.) and flip-flops. composition. The switch matrix is ​​highly flexible and can be configured to handle combinatorial logic, shift registers or RAM. In Xilinx's FPGA devices, the CLB consists of multiple (typically four or two) identical slices and additional logic, as shown in Figure 2-5. Each CLB module can be used not only to implement combinatorial logic, timing logic, but also as distributed RAM and distributed ROM.

CLB structure diagram

Figure 2-5 Schematic diagram of a typical CLB structure
Slice is the basic logical unit defined by Xilinx Company. Its internal structure is shown in Figure 2-6. A slice consists of two 4-input functions, carry logic, arithmetic logic, storage logic and function multiplexer.

Typical 4-input Slice structure diagram

Figure 2-6 Schematic diagram of a typical 4-input Slice structure
The arithmetic logic consists of an exclusive OR gate (XORG) and a special AND gate (MULTAND). An XOR gate can enable a slice to achieve a 2-bit full-add operation. A dedicated AND gate is used to increase the efficiency of the multiplier. The carry logic is a dedicated carry signal. Compatible with function multiplexer (MUXC) for fast arithmetic addition and subtraction operations; 4 input function generator for 4 input LUT, distributed RAM or 16-bit shift register (Slice in Virtex-5 series chip) The two input functions are 6 inputs, which can implement a 6-input LUT or a 64-bit shift register. The carry logic includes two fast carry chains to improve the processing speed of the CLB module.

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