As cars enter thousands of households, how to safely and conveniently park cars has become a common problem faced by many drivers. The car surround system design collects the video information of four cameras in front and rear of the vehicle, and combines the video information obtained by the four cameras into a coherent 360-degree circular image through video processing technology to achieve 360-degree safe driving without dead angle.
One. Overview of car surround system design
The traditional parking system mainly enables the driver to see the rear of the car through three means, namely the reverse mirror, the reversing radar and the reversing camera. However, all three methods have this blind spot on the side of the car. For some more complicated road sections, the driver can only see the front and rear direction, while the sides of the car body are easily scratched by the roadside foreign objects.
Therefore, research and development of automotive 360° viewing system has high prospects and applicability. This project uses Xilinx Spartan 6 FPGA for algorithm development and system control.
two. System function description
System functions
According to the design goals of this project, the functions that this design needs to accomplish are:
1. Collecting the image information of four cameras in front of and behind the car
2. The video information obtained by the four cameras is spliced ​​into a 360-degree viewing image through video processing technology.
3. 360 degree view image needs to be coherent, can not feel the obvious stitching signs
Time performance
According to the design goals of this project, the car surround system should be able to process continuous video frame images in real time to ensure the safety of car driving.
three. Design
Analysis of system working principle
In order to achieve the 360° panoramic target, each camera must have a viewing angle of more than 90°, so we designed a wide-angle fisheye lens with a viewing angle of 170 degrees.
In use, because the lens angle is large enough, the images of different cameras will overlap partially, so that as long as the position of the camera is properly configured and the overlapping parts are properly spliced, the 360-degree viewing angle can be recovered from the images of the four cameras. image.
Overall structure of the system
This system uses Xilinx Spartan 6 FPGA to develop system control and image processing algorithms. According to the analysis of system functional requirements and performance requirements, the system block diagram can be obtained as follows:
Figure 1: Block diagram of the car surround system
As can be seen from the figure, the system is mainly composed of three parts, namely camera (4), signal processing and display. The video signal collected by the camera is sampled and sent to the signal processing part for image processing and splicing, and finally sent to the VGA liquid crystal display.
System solution hardware design
The system hardware design is shown below:
Figure 2: Hardware design of the car surround system
The camera captures the image signal and sends it to the ADV7184 for PAL signal decoding. The decoded digital signal is sent to the Spartan-6 FPGA for various image processing. After the completion, the RGB signal is sent to the ADV7123 for VGA format video output.
The ADV7184 is an integrated video decoder that automatically detects standard analog baseband TV signals compatible with NTSC, PAL and SECAM standards worldwide and converts them to 4:2 compatible with 16- or 8-bit CCIR 601/CCIR 656 : 2 component video data.
Spartan – 6 is the core device of this system and has the following features:
Designed for low cost design
Very low static and dynamic power consumption
Multi-voltage, multi-standard SelecTIO? Interface bank
High efficiency DSP48A1 slice
High performance arithmetic and signal processing
Fast 18 x 18 multiplier and 48-bit accumulator
Pipeline and cascading functions
Pre-adder for assisting filter applications
Integrated memory controller module
LUT designed for pipelined applications with dual triggers
Block RAM with various granularities
Low noise, high flexibility clock control
The ADV7123 is a high speed digital to analog converter with three high speed, 10-bit video DACs with complementary outputs, a standard TTL input and a high impedance, analog output current source for driving the VGA output. It has the following characteristics:
Throughput: 330 MSPS
Three-channel, 10-bit digital-to-analog converter
Spurious free dynamic range (SFDR)
RS-343A/RS-170 compatible output
Complementary output
DAC output current range: 2 mA to 26 mA
TTL compatible input
System software design
The conversion between YCrCb and RGB is as follows:
Figure 3: Software design of car surround system
As shown in the figure, the working of the viewing system is divided into 8 steps. Among them, YCrCb to RGB system conversion, image denoising, shape correction, image cropping and splicing are all completed by FPGA.
1. After the ADV7184 is decoded, the YCrCb signal is output. In order to facilitate the subsequent processing, it is converted into RGB format.
2. Since the camera (such as CCD) will introduce noise more or less during imaging, especially when the brightness of the scene is insufficient, the noise will be obvious, which will affect the subsequent processing. Therefore, the converted signal needs to be denoised.
3. Due to the use of the fisheye lens, the part at the edge will be deformed, so shape correction is required.
4. After the previous steps have been processed, the image can be cropped and stitched. There are many ways to splicing images. Here you can calculate the shape required for each lens, and then cut and splicing according to the calculation results.
Application programs are normally developed in the CPU`s RAM memory and executed from RAM memory. If additional program integrity is desired, or operation of the PLC without a battery is desired, an optional EEPROM or EPROM can be installed in a spare socket (labeled PROGRAM PROM) on the Model 311/313 backplane or in a socket on the model 331/341 CPU Module. EEPROMs can be written to and read from. EPROMs can be read when installed in the PLC; however, they must be written to using an external PROM programming device. Following is the procedure for adding or changing the EEPROM or EPROM. For clarity, the term PROM is used to refer to either an EEPROM or an EPROM. 1. Remove power from the system. 2. If 311/313 Remove all modules, including the power supply. Remove the plastic cover. 3. If 331/341: Remove CPU from backplane. Remove front plate and bezel. Unsnap circuit board and remove from case. 4. If the socket is the type which has a screw near the top edge (some versions of 311/331), loosen screw at top of PROM socket (CCW twist;). 5. If present, remove old PROM from socket. Replace with or install new PROM. Orient the PROM so the end with a notch (the top of the prom) is toward the top edge of the backplane. Pin 1 of the prom is the first pin on the left as you move counter–clockwise from the notch. On the 311/331, correct installation orients the notch toward the screw.
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