Network-on-chip (NoC) is a new system-on-chip design method used in large scale integrated circuit (VLSI) systems. In an on-chip network system, processor cores, memory, and dedicated intellectual property cores are connected to each other over a network rather than through the current common shared bus-based approach. An on-chip network system consists of several data links. These data links are interconnected by an on-chip network router to form a network. Various modules are connected to the network through a network interface (NIC). Since the router can perform routing decisions and temporary storage and forwarding of messages, the information can be forwarded from any source module through several data connection transmissions and routers to any destination module. It can be seen that the on-chip network system introduces the concept of the macro communication network we use every day into on-chip, inter-module communication. Both are transmitting information on a multiplexed data link.
The on-chip network design method can break through the technical bottleneck of many traditional integrated circuit design methods. Conventional integrated circuit design methods use point-to-point dedicated wires between the two modules. When the scale of integrated circuits is expanded to a certain extent (for example, integrated transistors reach 1 billion), the drawbacks and limitations of traditional design methods are gradually highlighted. First, the connection between the modules will occupy a large amount of chip area. Secondly, the traditional design method adopts the global unified clock. As the chip scale increases and the speed increases, the huge clock tree will not guarantee the unification of the global clock, and the clock tree itself will generate a large amount of energy consumption. In addition, in order to cope with the increasing demand for multi-function and parallelism of chips, the number of modules in large-scale integrated circuits will further increase, and the traditional integrated circuit design methods in wiring, reusability, scalability, etc. Faced with more serious challenges.
Due to the use of multiplexed data links and packet-switched communication structures, the design method of the on-chip network can better solve the above problems. The modules in each chip, like the hosts in the Internet, access the network through a standardized network interface (NIC) and communicate with the destination module using shared network resources. This parallelism and scalability are fully guaranteed. Secondly, an important feature of the on-chip network method is the design concept of GALS (Globally Asynchronous Local Synchronous), which avoids the generation of a huge clock tree and solves the synchronization problem. In addition, since the on-chip network method realizes the separation of computing resources (each processing, computing, storage module) and communication resources (network) in the chip, the communication network is transparent to a single module, and the modules are designed independently of each other. This largely complies with the modular trend in integrated circuit design.
In the past few years, some research institutes have proposed research on the verification methods of different levels of NoC. The general NoC verification is based on software simulation and modeling, such as C-, C++, Systemc for system-level modeling and simulation. The verification is very flexible, but it is very expensive in simulation time. Because the actual application cannot be run, the entire NoC system cannot be verified (such as IP core verification) and only the NoC interconnection network can be verified. At the same time, software verification is a synthetic traffic generator. Although it can flexibly verify the power and performance of NoC under different network parameters, it relies too much on many approximations and assumptions to affect the accuracy of the results. On the other hand, software simulation relies on simple traffic generators, so that their verification results do not provide real value, because the performance and power consumption of the network is heavily dependent on the traffic characteristics of the services actually running on the network. While some applications can be described using a high-level abstraction model of software validation, this is only suitable for a few cases. Therefore, in order to obtain meaningful results, prototype verification in practical applications is very necessary.
Prototyping on an FPGA meets these requirements, providing faster speed and greater accuracy. As a kind of on-chip application technology, NoC needs to be implemented in hardware. Software verification can not take into account the physical characteristics of hardware (such as gate delay) but theoretically accurate cycle, which may lead to theoretically correct. The result is not operational on actual hardware, and FPGA prototyping does not have these problems. The FPGA prototype allows a designer to evaluate all aspects of the design, explain the main ideas, and provide predictions about the final reality of the product implementation, such as making accurate area estimates feasible, as well as actual hardware cost estimates and energy consumption for each component. measuring.
As FPGAs entered the market, it gradually replaced ASICs. The FPGA design cycle is short, while the NRE cost is small, and its fast reconfiguration, so FPGA usage is very common. The FPGA's chargeable configuration performance is fine-tuned at a time based on changes in system requirements, so it provides a very versatile platform. The NoC has a modular nature, so it can be re-used with minor modifications depending on the application requirements, so prototyping the NoC on the FPGA is very suitable.
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