Because many children's shoes universities learn "microcomputer principle" are soy sauce, when the teacher is flies on the podium, the basic knowledge of MMU is not clear, so the understanding of the computer is a mess, Linux can not learn. Then I was often asked about a variety of wonderful memory management problems that made people vomit blood. These problems show that these children's shoes are not clear about the most basic MMU and page table working mechanism. I feel that I have to write something to make these children's shoes soy sauce, and to stabilize the basic horse steps. Of course, this is not for others, nor for selfless dedication. It is purely to avoid being asked to vomit blood many times. Sooner or later. One day he vomited blood and died. In order to be able to live longer, this article is specially made.
Assume that the page table has only one level
For a CPU with an MMU, after the MMU is turned on, the CPU is addressed as follows: At any time, the CPU sends out the address as a virtual address. After the virtual address is sent to the MMU, the MMU uses the page table to page. The physical address corresponding to the virtual address is found in the table, so that the external memory is accessed. The page table address register in the MMU records the storage location of the page table itself.
Now let's assume that the size of each page is 4KB, and assuming that the page table has only one level, the page table grows like this, and each row of the page table is 32 bits.
When the CPU accesses the virtual address 0, the MMU will check the 0th line of the above page table and find that the 0th line does not hit, so the MMU will give the CPU no matter what form (R read, W write, X execution) access. When a page fault is issued, the CPU automatically jumps to the fault code to process the fault.
When the CPU accesses the virtual address 4KB, the MMU will check the first line of the above page table (4KB/4KB=1) and find the first line hit, if this time
If the user performs reading or execution, the MMU accesses the 6MB address of the memory stick, because the permission to record the page in the page table is RX;
The user is going to write 4KB. Since the permission in the first line of the page table is RX, and the permission you have written is not recorded, the MMU will issue a page fault to the CPU, and the CPU automatically jumps to the fault code to process the fault.
When the CPU accesses the virtual address 8KB+16, the MMU will check the second line of the above page table (8KB/4KB=2) and find that the second line hits the physical address 8M. At this time, the MMU will access the 8MB of the memory. +16 this physical address. Of course, permission checks are also needed.
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When the CPU accesses the virtual address 3GB, the MMU will check the 3GB/4KB line of the above page table. The record in the table is hit. It is found that the physical address corresponding to the virtual address 3GB is 0, so the MMU accesses the address on the memory stick. 0. However, this access is divided into 2 cases:
When the CPU executes the user mode program, it accesses 3GB. Since the U+K permission recorded in the page table is only K, the U is not authorized. The MMU will issue a page fault to the CPU, and the CPU automatically jumps to the fault code to process. Fault
When the CPU executes the kernel mode program, it accesses 3GB. Since the U+K permission recorded in the page table has only K, K has permission. The MMU does not issue a page fault to the CPU, and the program executes normally.
It can be known that if the page table has only one level, each 4KB of virtual address space requires a row (32bit) in the page table, then the CPU needs to cover the entire 4GB of memory, the size of the page table is:
4GB/4KB *4 = 4MB.
Note that the page table is seamless and full coverage! ! ! Your page table does not cover all, when the CPU accesses the virtual address, the MMU does not know where to look....
Therefore, the size of this page table is 4MB, covering the entire 0-4GB virtual address space. Any virtual address can use the upper 20 bits of the address (since one page is 4KB, the lower 12 bits are offset within the leaf). ), as the page number of the table table to read the corresponding page table entry.
This process of checking the water meter is done automatically by the MMU hardware.
Now let's assume that there are 2 processes in Linux, one is QQ and the other is Firefox. Their page tables are as follows:
When the CPU is executing QQ, Linux will fill the physical address of the QQ page table 255MB into the MMU's page table address register. At this time, the QQ page table takes effect. According to the contents of the page table, if the CPU accesses the virtual address of 4KB, the MMU accesses the 6MB physical address of the memory module; if the CPU accesses the virtual address of 8KB, the MMU accesses the 8MB physical address of the memory module; if the CPU accesses the virtual address of 3GB, The MMU accesses the 0MB physical address of the memory module;
When the CPU is executing Firefox, Linux will fill the physical address of the Firefox page table 280MB into the MMU's page table address register. At this time, the Firefox page table takes effect, and the QQ page table fades out. According to the contents of the page table, if the CPU accesses the virtual address of 4KB, the MMU accesses the 100MB physical address of the memory module; if the CPU accesses the virtual address of 8KB, the MMU accesses the physical address of the memory of 200MB; if the CPU accesses the virtual address of 3GB, The MMU accesses the 0MB physical address of the memory module.
Above we found a common point, QQ and Firefox to access the 3GB virtual address, the final MMU access is 0MB physical address, the specific reason is very simple, QQ and Firefox, these two page tables, 3GB / 4KB this line It fills in exactly the same stuff.
Multi-level page table: the real existence in
Above we found that if a first-level page table is used, each process needs a 4MB page table. This space is still a lot of waste, so we can use a secondary or tertiary page table. For example, suppose we use the upper 10 bits of the address as the index of the primary page table, and the middle 10 bits as the index of the level 2 page table. The CPU accesses the virtual address 16, and if this address is decomposed into 10/12 bits, it looks like this:
Then the MMU will use the 0 subscript to access the first page of the primary page table (the address of the primary page table is filled in the MMU's page table address register), the content of the 0th line is 2MB (here is no longer The final physical address, but the physical address of the secondary page table, proves that the address of the secondary page table is 2MB, so the MMU automatically goes to the middle 10 bits as the subscript to query the secondary page table at 2MB. In the level 2 page table, the physical address of the virtual address of page 0 (address range 0x00000000~0x00000FFF) is finally 1GB, so the MMU accesses the physical address of 1GB+16 of the memory.
According to the above analysis, the memory occupied by the level 1 page table is 2 to the power of 10, and multiplied by 4, that is, 4 KB. And each secondary page table is also 2 to the 10th power, and then multiplied by 4, which is 4KB. The main advantage of the grading mechanism is that the secondary page table does not necessarily exist, for example, the second row of the primary page table does not hit, that is, the following addresses are invalid:
Then the corresponding secondary page table of this row is not needed, so the memory usage of the 4KB secondary page table in this interval is saved. The page table is of course three or more.
As for the multi-level page table, in fact, the MMU only needs to know the base address of the first-level page table. Each time the process is switched, the address of the first page table is refilled into the MMU, and the page table of the new process is activated.
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