74hc138 3-8 line decoder / resetter
Texas Instruments CD74HC138, CD74HC238 and CD74HCT138, CD74HCT238 are high speed silicon gate CMOS decoders for memory address decoding or data routing applications.
Hc138 The principle of operation is high-performance memory decoding or data transmission system requiring short transmission delay time. In high-performance memory systems, the efficiency of the decoding system can be improved by using such a decoder. When the fast enabling circuit is used in the high speed memory, the delay time of the decoder and the enabling time of the memory are usually smaller than the typical access time of the memory, which is to say that the system is translated by Schottky clamp. The effective system delay caused by the encoder is negligible. The HC138 translates one of the eight outputs according to the three-digit binary input code and the enabling input conditions.
Low level output. Two active-low enable inputs and an active-high enable input reduce the external gate or inverter required for expansion, extending to a 24-wire decoder without external gates; expansion to 32 The line decoder only needs to connect an external inverter. In demodulator applications, the enable input can be used as a data input.
Figure 1 pin diagram Figure 2 function diagram
Figure 3 test circuit and waveform
Application circuit:
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